| Submission Open for Jan-Dec-2024 |
| Last Date of Submission : |
| 20th, April-2024 |
| Acceptance Notification : |
After Peer Review |
| Last Date of Publication : |
| 30th, April-2024 |
Volume10 ISSUE 1 Call for Conference Special Issue Archive (Recent Update ISSUE)
| S.NO | TITLE | PAGE NO | DOWNLOAD | |
| IJVDCS 46 | Design of Implementation of Enhanced High Speed 8-Bit Vedic Multiplier Using Barrel Shifters Authors:ABHILASH ANUMULA, UMAR FAROOQ |
0235-0239 |
Download | |
| IJVDCS 47 | Prefix Parallel Adder Implementation 128-Bit using on Verilog Authors:A. DEEPIKA, K.JOSHNA |
0240-0243 |
Download | |
| IJVDCS 48 | Comparison of Vedic Multiplier with Conventional Array and Wallace Tree Multiplier Authors:ANU THOMAS, ASHLY JACOB, SERIN SHIBU, SWATHI SUDHAKARAN |
0244-0248 |
Download | |
| IJVDCS 49 | Design and Implementation of High Speed MAC Unit using Carry Select Adder Authors:K. CHANDRA SEKHAR, K. S. VINOD KUMAR, P. LAKSHMI MOUNIKA, CH. AMULYA VARDHINI, D. JEEVAN |
0249-0251 |
Download | |
| IJVDCS 50 | Low-Power and Area-Efficient Carry Select Adder Authors:BSSV RAMESH BABU, M. UDAY KUMAR, K. VENUGOPAL, B. BABJI |
0252-0255 |
Download | |
| IJVDCS 51 | GDI Techniques for Low Power Digital Circuits Authors:A. SAIRAMYA, M. UDAY KUMAR, M. VAMSI PRIYA, K. SUSHMA, CH. SRINIVAS RAO |
0256-0260 |
Download | |
| IJVDCS 52 | Implementation of Reed Solomon Decoder for Area Critical Applications Authors:M.BHAVANI, C.RAMMOHAN |
0261-0267 |
Download | |
| IJVDCS 53 | High-Speed and Energy-Efficient Carry Skip Adder using Skip Logic Authors:K. RAMASAGAR REDDY, KRISHNA NAIK DUNGAVATH, V. VIJAYALAKSHMI, S. RAVI KUMAR |
0268-0270 |
Download | |
| IJVDCS 54 | Data Encoding Techniques for Reducing Energy Consumption In Network-On-Chip Authors:KOTA ANITHA, ARUN PRASAD TANGUTURI |
0271-0276 |
Download | |
| IJVDCS 55 | Design and Implementation of a Low Voltage Power Double Tail Comparator using Digital Schematic Circuits Authors:PUJITHA. B, T. CHAKRAPANI |
0277-0282 |
Download | |
